Measurement-computing CIO-PDMAxx Manuel d'utilisateur télécharger pdf (Page 22)

This bit is set when in REP_ENB mode, and the Sample

Counter has reached terminal count.

REP_DONE0

This bit is set when in REP_ENB mode and the FIFO is

half-full.

REP_FLG1

This bit is set when in REP_ENB mode and the FIFO

has been overrun. This flag indicates that the FIFO is

being loaded too quickly

OVERRUN2

This bit is set when in REP_ENB mode and the FIFO

has been underrun. This flag indicates that the FIFO is

being unloaded too quickly.

UNDERRUN3

1=Interrupt Pending, 0 = No InterruptIRQ7

DescriptionNameBit

5.2.9 FIFO Clear Start Address Register

This is a write only register. A write to this register clears the FIFO address pointers to

zero. Data is don’t care. Prior to initiating a REP-STRING transfer the FIFO write and

read address pointers should always be cleared to a start address of 0.

Base Address + Bh

XXXXXXXX

01234567

MSB LSB

5.2.10 REP String Control Register

This is a read/write register. These bits are in the inactive reset state after power-up.

Base Address + Ch

ERR_ENBDBL_

BUFF

HALF_

FF_CNT

REP_

CONT

REP_

ENB

REP_

MODE

01234567

MSB LSB

1 2 ... 17 18 19 20 21 22 23 24 25 26 27 ... 31 32

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Measurement-computing CIO-PDMAxx Manuel d'utilisateur Page 22