Measurement-computing CIO-PDMAxx Manuel d'utilisateur télécharger pdf (Page 14)

The DMA control register is cleared on power-up or hardware reset. If you are

writing your own DMA routine, the DMA enable bit should be set before enabling the

8237 mask register.

DMA level selected by the DMA LEVEL bit is tri-stated when DMA ENABLE = 0.

Take care when writing to AUX1 and AUX2 that the current contents of the DMA

5.1.3 INTERRUPT CONTROL REGISTER

Interrupt control

BASE ADDRESS + 3 302h, 770

N/AN/AN/APin 26N/AN/AN/AN/A

SLOPEINT

SRC

INT

SRC

AUX 3IR LEVIR LEVIR LEVINT

ENABLE

01234567

Negative edge1

Positive edge0SLOPE

8237 terminal count11

8254 timer10

8237 terminal count01

External input00INT SRC (SOURCE)

Output only on pin 26XAUX 3

Level 7111

Level 6110

Level 5101

Level 4100

Level 3011

Level 2010

Inactive001

Inactive000IR LEVEL

Enabled1

Disabled0INT ENABLE

FUNCTIONVALUEBIT NAME

The interrupt control register is cleared on power-up or hardware reset. If you are

writing your own interrupt routine, set the interrupt enable bit before enabling the

8259 mask register. The interrupt level selected by the IR LEVEL bit is tri-stated

when IR ENABLE = 0.

When writing to AUX1 and AUX2, take care not to disturb the current contents of the

INTERRUPT REGISTER.

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 31 32

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Measurement-computing CIO-PDMAxx Manuel d'utilisateur Page 14