
PCI-DAS1602/16 User's Guide Specifications
25
Counter
*Note: Pins 21, 24, and 25 are pulled to logic high via 10K resistors.
Table 11. Counter specifications
Two 82C54 chips containing three 16-bit down counters each
Counter 0 — ADC residual sample
counter.
Gate: Programmable source.
Output: End-of-Acquisition interrupt.
Counter 1 — ADC pacer lower
divider
Source: 10 MHz oscillator
Gate: Tied to Counter 2 gate, programmable source.
Output: Chained to Counter 2 Clock.
Counter 2 — ADC pacer upper
divider
Source: Counter 1 Output.
Gate: Tied to Counter 1 gate, programmable source.
Output: ADC Pacer clock (if software selected), available at user
connector.
Counter 0 — pretrigger mode
Output: End-of-Acquisition interrupt.
Counter 0 — non-pretrigger mode:
user counter 4
Source: User input at 100pin connector or internal 10MHz (software
selectable)
Gate: User input at 100pin connector.
Output: Available at 100pin connector.
Counter 1 — DAC pacer lower
divider
Source: 10 MHz oscillator
Gate: Tied to Counter 2 gate, programmable source.
Output: Chained to Counter 2 Clock.
Counter 2 — DAC pacer upper
divider
Source: Counter 1 Output.
Gate: Tied to Counter 1 gate, programmable source.
Output: DAC Pacer clock, available at user connector.
High pulse width (clock input)
Low pulse width (clock input)
2.0 volts min, 5.5 volts absolute max
0.8 volts max, -0.5 volts absolute min
Crystal oscillator frequency
Power consumption
Table 12. Power consumption specifications
+5 V operating (A/D converting to FIFO)
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