Measurement-computing ADAC/5500 Series Manuel d'utilisateur télécharger pdf (Page 54)

Gain/Channel Selection: 256 element RAM

Data Format: 16-bit right justified

6.3.2 A/D Trigger – ADAC/5503HR and ADAC/5504HR

Clock Sources: - software

- on-board programmable pacer

- user defined external TTL

External Clock Input Delay: - 100ns uncertainty

Trigger Sources: - software

- on-board pacer (burst mode)

- external (TTL)

Triggering Modes: - software gate

- external gate

- periodic burst

- pre-trigger (sample until trigger)

- post-trigger (sample after trigger)

- about-trigger (sample before and after trigger)

External Trigger Input Delay: - 100ns uncertainty

6.3.3 D/A Outputs ( -V Option only) – ADAC/5503HR and ADAC/5504HR

Number of Outputs: 2 (optional) Clocked DACs

Resolution: 16 bit (152.800 µV/bit on 0 to 10 V range)

D/A Full Scale Range: ±10 V, 0 to 10 V

Settling time to 0.006% of FSR: 10 µsec for 20 V step

Differential Linearity: ± 0.25 LSB @ 25° guaranteed monotonic

Relative Accuracy

Bipolar: ± 2 LSB typ.

Unipolar: ± 4 LSB typ.

Gain Error: Adjustable to zero

Zero Error: Adjustable to zero

Data Coding

Unipolar: Straight binary

Bipolar: Offset binary 2's complement

Data Format: 16 bit right justified

Data Storage: FIFO

DAC Clock Update Source: - Software Pacer

- Internal Pacer

- External TTL

ADAC Series 908196 -49- ADAC/5500 Series User’s Manual

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Measurement-computing ADAC/5500 Series Manuel d'utilisateur Page 54