Measurement-computing CIO-DAS-TEMP Manuel d'utilisateur Page 16

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Table 5-2. Prescalar Divider/2 MHz Clock Control Codes
61.01111115,6251110
122.07011131,2500110
244.14101162,5001010
488.280011125,0000010
976.561101250,0001100
1,9530101500,0000100
3,906.251001None1000
7,812.50001None0000
Output FreqP0P1P2P3Output FreqP0P1P2P3
When TMRE = 0, the Prescaler and Counter 2 are disabled. When TMRE = 1, the prescaler and Counter
2 are enabled.
IR2
IR1 IR0 Hardware IRQ
0 0 0 Disable interrupts
0 0 1 Disable interrupts
0102
0113
1004
1015
1106
1117
BASE + 5 Read - Read bit settings
IR0IR1IR2TMREP0P1P2P3
01234567
BASE + 6 Write - Load counter 0
A write to this address loads the v alue 65,535 into counter 0. T his must be done before trig gering a
conversion.
BASE + 7 Not used
12
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